微电子专业英语翻译The 3D integrated circuit (3D IC) is an emerging te

微电子专业英语翻译
The 3D integrated circuit (3D IC) is an emerging technology that vertically stacks
multiple die with a die-to-die interconnect as illustrated in Fig. 10.1. The die-to-die
via pitch is very small and provides the possibility of arranging digital functional
unit blocks across multiple die at a very fine level of granularity. This results in
a decrease in the overall wire length, which translates into less wire delay and less
power. Thus, 3D ICs can address the wire delay problem effectively by replacing the
long and slow global interconnects with short and fast vertical routes. Advances in
3D integration and packaging are undoubtedly gaining momentum and have become
of critical interest to the semiconductor community. These 3D integrated circuit and
package manufacturing technologies are rapidly being adopted by several leading
companies for commercial applications.
The location of individual micro-architectural modules plays a significant role on
many important metrics. First, floorplanning has a huge impact on the performance
of a given micro-architecture [measured by instructions per cycle (IPC)] as the
global interconnects between modules are likely to be pipelined in order to meet
high target clock frequencies. This may increase or decrease the access latency
on all inter-module interconnects. Second, the thermal and leakage profile is
highly correlated to the floorplan. This is because the temperature of each microarchitectural
module is not solely dependent on the heat generation rate of each
individual module but also the heat coupling between its neighboring modules.
Moreover, the leakage power of each transistor is exponentially proportional to the
temperature. Third, floorplanning affects the dynamic power consumption of the
buses and clock distribution network. The total number of flip-flops (FFs) inserted
on global interconnects changes the dynamic power consumed by the clock distribution
network. However, the performance and thermal objectives are conflicting with
each other since shorter distance among the hot modules improves the performance
while exacerbating the thermal issue. To address the different design constraints of
different domains, we need a goal-directed, automated floorplanner that allows users
to weight their own design requirements and make effective design tradeoffs. The
following specific topics are covered in this chapter

这句没有彻底搞懂，其他都ok ：The die-to-die via pitch is very small and provides the possibility of arranging digital functional unit blocks across multiple die at a very fine level of granularity
die-to-die后面省略了什么？die-to-die interconnect ？
via pitch 指的是什么？via是介词，不是形容词吧？
digital functional unit blocks 是不是指的 控制电路而非运算电路？ 比如时钟系统什么的？
at a very fine level of granularity 是不是小制程的意思？
3D集成电路封装技术属于新兴科技，如图10.1所示，它是几个互联芯片在垂直方向上的堆栈/堆叠。芯片间的跨距非常微小，使得芯片之间的数字功能单元能够集成进来。这样的好处是缩短了连接线总长，从而降低线路延迟、能耗更低。
3d芯片由于采用了短程、快速的垂直连线，能够很好的解决此前因为冗长、慢速的全局连线所带来的线路延迟问题。3d集成和封装技术发展势头很猛，已成为半导体业界的宠儿。几大芯片公司争相在其商用领域的产品上采用3d封装工艺。
单个微架构模块在电路中的位置能直接影响到芯片的很多性能。第一，芯片布局（各模块的几何架构及互联线路？？）直接影响芯片的运算性能[周期指令量(IPC)]，因为要获得更高的目标时钟频率，就要在不同模块间架设互联线路。这会提高也可能降低线路延迟。 第二，散热和耗散问题和芯片布局息息相关。这是因为单个微架构模块的温度并不只是取决于自身的发热量，也取决于其周围的模块单元对其造成的影响。
此外，每个晶体管的耗散功率会随着温度的升高而几何增长。第三，芯片布局影响到总线和时钟分配网络的动态能耗。整合到全局互联电路中的触发器的数量也会对时钟系统的能耗产生影响。尽管如此，性能和发热量总是冲突的，各个发热元件的距离越近，性能会提升的同时对温度控制的要求就更高。不同的应用会有不同的设计局限，因此我们需要一个面向目标的，自动的芯片布局规划器，允许用户根据自身的设计需求，找到有效的折衷方案。本节会讨论以下相关议题。