vhdl VHDL error at dt.vhd(25):can't determine definition of
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vhdl VHDL error at dt.vhd(25):can't determine definition of operator ""="" -- found 0 possible de
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dt is
port(clk,ope,close:in std_logic;
up1,up2,down2,down3:in std_logic;
stop1,stop2,stop3:in std_logic;
y:out std_logic_vector(7 downto 0));
end dt;
architecture one of dt is
type zt is(wait1,wait2,wait3,stop,open1,open2,open3,open4);
signal up11,up22,down22,down33,stop11,stop22,stop33,ope1,close1:std_logic;
signal lt,st:zt:= wait1;
begin
process(up1,up2,down2,down3,up1,up2,down2,down3,ope,close)
begin
up11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dt is
port(clk,ope,close:in std_logic;
up1,up2,down2,down3:in std_logic;
stop1,stop2,stop3:in std_logic;
y:out std_logic_vector(7 downto 0));
end dt;
architecture one of dt is
type zt is(wait1,wait2,wait3,stop,open1,open2,open3,open4);
signal up11,up22,down22,down33,stop11,stop22,stop33,ope1,close1:std_logic;
signal lt,st:zt:= wait1;
begin
process(up1,up2,down2,down3,up1,up2,down2,down3,ope,close)
begin
up11
你在不同的进程中,对同一个信号(例如stop11、stop22、stop33等)进行赋值,这是VHDL所不允许的;而且在同一个进程中,也不允许对同一个信号多次赋值(例如第二个进程中的stop22).
再问: 谢谢了,不过我想说如果在一个进程里反复赋值,是对离end process最近的那个起作用。。
再答: 我刚试了一下,确实如你所说。 在一个进程中,对同一个信号多次赋值,我以前没试过,是因为我想像不出这类描述的物理含义。
再问: 谢谢了,不过我想说如果在一个进程里反复赋值,是对离end process最近的那个起作用。。
再答: 我刚试了一下,确实如你所说。 在一个进程中,对同一个信号多次赋值,我以前没试过,是因为我想像不出这类描述的物理含义。
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