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英文文献翻译,牛人帮帮忙,翻得好再加分
While using common parallel AER interfaces for connecting to the locally attached chip, we use a novel serial AER interface with flow-control. With this interface running at a bit clock of up to 3.125GHz we achieve event rates of up to 78.125MHz for 32bit AEs.
The parallel AER interface allows for event rates of up to 20 to 30MHz. This is in practice reduced by the signal propagation delays induced by the PCB traces and especially when used with ribbon cables.
For sending monitored AEs to a PC and reading AEs to be sequenced back from it we implemented a USB2.0 interface. Here we achieved bandwidths of 40MB/s, only limited by the USB host-controller on the computer itself. This allows for an event rate of 5MHz with 64bit timestamped AEs.
Given the filtering capabilities of the FPGA's routing fabric we can easily select parts of the address space we are interested in for monitoring, and because of the large buffers for monitored data on the FPGA itself we can compensate for the fact that the FPGA to PC interface is a lot slower than the parallel and serial AER interfaces.
The very high speeds of the serial AER interface allows us to have very low latency in serial AER links, and these links allow for the construction of very large multi-chip address event systems, e.g. by daisy-chaining multiple AEX boards.
ACKNOWLEDGMENT
Some of the ideas presented in this work were inspired by dis¬cussions held at the Telluride Neuromorphic Engineering Workshop. Particularly helpful suggestions were provided by V. Dante, ISS Italy, and A. linares-Barranco, Universidad de Sevilla, Spain. We wish to also thank N. Felber, D-ITET ETHZ for supporting us regarding design aspects and U. Breu, C. Flaig, D. Flatz & A. Lehmann for proofreading. This work was supported in part by the EU grant DAISY (FP6-2005-015803).
While using common parallel AER interfaces for connecting to the locally attached chip, we use a novel serial AER interface with flow-control. With this interface running at a bit clock of up to 3.125GHz we achieve event rates of up to 78.125MHz for 32bit AEs.
The parallel AER interface allows for event rates of up to 20 to 30MHz. This is in practice reduced by the signal propagation delays induced by the PCB traces and especially when used with ribbon cables.
For sending monitored AEs to a PC and reading AEs to be sequenced back from it we implemented a USB2.0 interface. Here we achieved bandwidths of 40MB/s, only limited by the USB host-controller on the computer itself. This allows for an event rate of 5MHz with 64bit timestamped AEs.
Given the filtering capabilities of the FPGA's routing fabric we can easily select parts of the address space we are interested in for monitoring, and because of the large buffers for monitored data on the FPGA itself we can compensate for the fact that the FPGA to PC interface is a lot slower than the parallel and serial AER interfaces.
The very high speeds of the serial AER interface allows us to have very low latency in serial AER links, and these links allow for the construction of very large multi-chip address event systems, e.g. by daisy-chaining multiple AEX boards.
ACKNOWLEDGMENT
Some of the ideas presented in this work were inspired by dis¬cussions held at the Telluride Neuromorphic Engineering Workshop. Particularly helpful suggestions were provided by V. Dante, ISS Italy, and A. linares-Barranco, Universidad de Sevilla, Spain. We wish to also thank N. Felber, D-ITET ETHZ for supporting us regarding design aspects and U. Breu, C. Flaig, D. Flatz & A. Lehmann for proofreading. This work was supported in part by the EU grant DAISY (FP6-2005-015803).
其他以匿名提问的也是你吗?
再问： 是同一个人，但是账号是我同学，你M我的我已经申诉了
再答： 在使用普通的并行AER接口以连接本机芯片时，我们使用一种新颖的，附带流量控制的串行AER接口。此接口在运行达至3.125GHz位时钟时，我们可实现32位AE的事件率高达78.125 MHz，而并行AER接口所允许的事件率只达到20至30 MHz。但是由于PCB串扰会引起的信号传播延迟，尤其是在使用带状电缆时，在实际操作时事件率会降低。 我们运用一个USB2.0接口来传送监控的AE至个人电脑及读取序列返回的AE。在此我们可以实现40MB/s的带宽，只受限于电脑本身的USB主机控制器；这使64位时间戳AE的事件率可达到5 MHz。 鉴于FPGA路由结构的过滤能力，我们可以很容易选择所要的地址空间进行监控；而FPGA本身监控数据的较大缓冲区，可以弥补其速度比并行与串行AE接口慢很多的缺点。 串行AE的超高速度允许我们的链接有很短的滞后时间，并且，这些链接容许建立巨大的多芯片AE系统，例如通过使用链式递增多路AEX板。 致谢 本项目里的一些创意是受到Telluride神经形态工程研讨会中讨论的启发；特别是意大利国家卫生研究所的V. Dante 和西班牙赛维利亚大学的A. linares-Barranc所提供的实用建议。我们也要感谢苏黎世联邦理工学院的N. Felber在设计方面所给予的支持，以及U. Breu,、C. Flaig、 D. Flatz和A. Lehmann先生为我们的文章进行校对。本项目的部分资助来自欧盟DAISY拨款(FP6-2005-015803)。 【英语牛人团】
再问： 是同一个人，但是账号是我同学，你M我的我已经申诉了
再答： 在使用普通的并行AER接口以连接本机芯片时，我们使用一种新颖的，附带流量控制的串行AER接口。此接口在运行达至3.125GHz位时钟时，我们可实现32位AE的事件率高达78.125 MHz，而并行AER接口所允许的事件率只达到20至30 MHz。但是由于PCB串扰会引起的信号传播延迟，尤其是在使用带状电缆时，在实际操作时事件率会降低。 我们运用一个USB2.0接口来传送监控的AE至个人电脑及读取序列返回的AE。在此我们可以实现40MB/s的带宽，只受限于电脑本身的USB主机控制器；这使64位时间戳AE的事件率可达到5 MHz。 鉴于FPGA路由结构的过滤能力，我们可以很容易选择所要的地址空间进行监控；而FPGA本身监控数据的较大缓冲区，可以弥补其速度比并行与串行AE接口慢很多的缺点。 串行AE的超高速度允许我们的链接有很短的滞后时间，并且，这些链接容许建立巨大的多芯片AE系统，例如通过使用链式递增多路AEX板。 致谢 本项目里的一些创意是受到Telluride神经形态工程研讨会中讨论的启发；特别是意大利国家卫生研究所的V. Dante 和西班牙赛维利亚大学的A. linares-Barranc所提供的实用建议。我们也要感谢苏黎世联邦理工学院的N. Felber在设计方面所给予的支持，以及U. Breu,、C. Flaig、 D. Flatz和A. Lehmann先生为我们的文章进行校对。本项目的部分资助来自欧盟DAISY拨款(FP6-2005-015803)。 【英语牛人团】