1.写一个带使能信号、清零信号、置数信号的六进制计数器的VHDL程序.2.由六进制、十进制计数器构成60进制

1.写一个带使能信号、清零信号、置数信号的六进制计数器的VHDL程序.2.由六进制、十进制计数器构成60进制

模多少的?任意?
我写了个模70的,如果要其他的自己修改参数就行了
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count_led is port(
rst,clk:in std_logic;
y:out std_logic_vector(13 downto 0));
end count_led;
architecture Behavioral of count_led is
signal oc:std_logic;
signal data:std_logic_vector(3 downto 0);
Signal Data1:std_logic_vector(3 downto 0);
Signal Data2:std_logic_vector(3 downto 0);
signal count_1:STD_LOGIC_vector (3 DOWNTO 0);
signal count_2:STD_LOGIC_vector (3 DOWNTO 0);
signal outdata1:std_logic_vector(6 downto 0);
signal outdata2:std_logic_vector(6 downto 0);
begin
count1:process(rst,clk)
begin
if (rst='1') then
count_1<="0000";count_2<="0000";
elsif (rising_edge(clk)) then
if (count_1="1001") then
count_1<="0000";oc<='1';
else count_1<=count_1+1;oc<='0';
end if;
if(oc='1')then
count_2<=count_2+1;
elsif (count_2="0110") then
count_2<="0000";
end if;
end if;
Data1<=count_1;Data2<=count_2;
end process;
led1:process(rst,clk)
begin
if (rst='1') then
outdata1<="0000000";
else if (rising_edge(clk)) then
case data1 is
WHEN "0000"=>outdata1<="1111110";
WHEN "0001"=>outdata1<="0110000";
WHEN "0010"=>outdata1<="1101101";
WHEN "0011"=>outdata1<="1111001";
WHEN "0100"=>outdata1<="0110011";
WHEN "0101"=>outdata1<="1011011";
WHEN "0110"=>outdata1<="0011111";
WHEN "0111"=>outdata1<="1110000";
WHEN "1000"=>outdata1<="1111111";
WHEN "1001"=>outdata1<="1111011";
when others=>outdata1<="0000000";
end case;
case data2 is
WHEN "0000"=>outdata2<="1111110";
WHEN "0001"=>outdata2<="0110000";
WHEN "0010"=>outdata2<="1101101";
WHEN "0011"=>outdata2<="1111001";
WHEN "0100"=>outdata2<="0110011";
WHEN "0101"=>outdata2<="1011011";
WHEN "0110"=>outdata2<="0011111";
WHEN "0111"=>outdata2<="1110000";
WHEN "1000"=>outdata2<="1111111";
WHEN "1001"=>outdata2<="1111011";
when others=>outdata2<="0000000";
end case;
end if;
end if;
end process;
y<=outdata2&outdata1;
end Behavioral;