verilog小程序求救

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verilog小程序求救
module abc(show_light,rst,clk);
input clk;
input rst;
output[3:0]show_light;
reg show;
reg aaa;
always@(posedge clk)
begin
if(aaa==0)
begin
aaa=1;
show=0;
end
else
begin
show=show+1;
end
end
always@(posedge rst)
begin
aaa=0;
end
assign show_light=show;
endmodule
出现如下问题：
Error (10028):Can't resolve multiple constant drivers for net "aaa" at abc.v(20)
Error (10029):Constant driver at abc.v(7)
Error:Can't elaborate top-level user hierarchy
Error:Quartus II Analysis & Synthesis was unsuccessful.3 errors,1 warning
Error:Peak virtual memory:150 megabytes
Error:Processing ended:Sat May 02 14:21:00 2009
Error:Elapsed time:00:00:03
Error:Total CPU time (on all processors):00:00:01
Error:Quartus II Full Compilation was unsuccessful.5 errors,1 warning

always@（posedge clk）
begin
singnal => ..;
end
在时序逻辑的赋值里面必须用阻塞赋值
而且一个always块操作一个被赋值信号!
修改前：
always@(posedge clk)
begin
if(aaa==0)
begin
aaa=1;
show=0;
end
else
begin
show=show+1;
end
end
修改后：
//for reg aaa
always@(posedge clk)
begin
if(aaa==0)
aaa《=1;
end
//for reg show
always@(posedge clk) begin
if(aaa==0)
show => 1'b0;
else
begin
show=>show+1;
end
end
请分清楚是同步reset还是异步reset
always@(posedge rst)
begin
aaa=0;
end
你这种写法会使编译器发疯的
想一想：如果posedge rst && aaa==0
然后aaa的值是多少?
所以你应该这么写
1.根据一个always块操作一个被赋值信号
always@(posedge clk or posedge rst)
if(rst)
aaa => 1'b0;
else
if (..)
...
else
...
end
最后一点,请把名字起得好一点通俗一点
别起什么aaa的破名字!

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