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vhdl求大神相助!\x05\x05\x05\x05\x05always @ (posedge left )\x05if

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vhdl求大神相助!
\x05\x05\x05\x05\x05
always @ (posedge left )
\x05if(!RST_N)DATA1 <= 9'd0;
\x05else
\x05DATA1 <= flag 0:DATA1 + 1;

\x05
always @ (posedge right)
\x05if(!RST_N)flag <= 0;
\x05else flag = flag;
vhdl求大神相助!\x05\x05\x05\x05\x05always @ (posedge left )\x05if
当posedge left变化时,(1)当!RST_N=’1‘则DATA1等于“000000000”,(2)当!RST_N=’0‘时,如果flag=1则将0赋予DATA1,flag=1则DATA1加1
当posedge right变化时,(1)当!RST_N=’1‘则flag赋予 0值,(2)当!RST_N=’0‘时,flag翻转(即0变1或者是1变0)